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RM0008
Figure 21. External interrupt/event GPIO mapping
EXTI0[3:0] bits in AFIO_EXTICR1 register
PA0
PB0
PC0
Interrupts and events
PD0
EXTI0
PE0
PF0
PG0
EXTI1[3:0] bits in AFIO_EXTICR1 register
PA1
PB1
PC1
PD1
EXTI1
PE1
PF1
PG1
EXTI15[3:0] bits in AFIO_EXTICR4 register
PA15
PB15
PC15
PD15
EXTI15
PE15
PF15
PG15
1. To configure the AFIO_EXTICRx for the mapping of external interrupt/event lines onto GPIOs, the AFIO
clock should first be enabled. Refer to Section 6.3.7: APB2 peripheral clock enable register
(RCC_APB2ENR) for low-, medium- and high-density devices and, to Section 7.3.7: APB2 peripheral clock
enable register (RCC_APB2ENR) for connectivity line devices.
The four other EXTI lines are connected as follows:
●
●
●
●
EXTI line 16 is connected to the PVD output
EXTI line 17 is connected to the RTC Alarm event
EXTI line 18 is connected to the USB Wakeup event
EXTI line 19 is connected to the Ethernet Wakeup event (available only in connectivity
line devices)
Doc ID 13902 Rev 9
177/995
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